RF Sampling ADCs – Challenges, Opportunities, and Implementations

The constant demand for higher throughput and bandwidth in next-generation wireless and wireline communications, such as 6G massive Multiple-Input Multiple-Output (MIMO) and Data Over Cable Service Interface Specification (DOCSIS) 4.0 over Hybrid Fiber Coax (HFC) networks, has triggered the need for multi-GS/s ADCs to digitize several GHz of bandwidth with high spectral purity and power efficiency. Low-power ADCs in deep-scaled CMOS are desirable to enable direct sampling at these frequencies, offering increased flexibility and integration capability with lower cost and footprint compared to traditional approaches. Time-interleaving seems to be the major solution to enable the required sample rates. However, the interleaver architecture determines the ADC performance to a large extent. Additionally, the bandwidth needs to be kept at a high level. This requires a high-bandwidth, linear analog front-end driving the ADC. This talk will delve into all these aspects and clarify them by showing recent developments.